Title:

Kind
Code:

A1

Abstract:

A discrete cosine transform system and discrete cosine transform method enables speeding up and restricts increasing of system scale size associating with speeding up in a system realizing discrete cosine transform and inverse discrete cosine transform for several kinds of different block sizes. The discrete cosine transform system has one ore more computing modes for performing one of discrete cosine transform and inverse discrete cosine transform for W points (N>W), in addition to a first computing mode for performing one of discrete cosine transform and inverse discrete cosine transform for N points. At least a part of computing units forming the system, may switch computing function in at least part of computing functions for performing discrete cosine transform and inverse discrete cosine transform for points other than N points, for performing the W point discrete cosine transform and inverse discrete cosine transform in parallel by the computing units forming the system.

Inventors:

Tajime, Junji (Tokyo, JP)

Application Number:

09/870689

Publication Date:

12/20/2001

Filing Date:

06/01/2001

Export Citation:

Assignee:

NEC CORPORATION

Primary Class:

International Classes:

View Patent Images:

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Primary Examiner:

NGO, CHUONG D

Attorney, Agent or Firm:

FOLEY & LARDNER LLP (WASHINGTON, DC, US)

Claims:

1. A discrete cosine transform system having one ore more computing modes for performing one of discrete cosine transform and inverse discrete cosine transform for W points which W is positive integer satisfying N>W, in addition to a first computing mode for performing one of discrete cosine transform and inverse discrete cosine transform for N points which N is positive integer, comprising: means provided at least a part of computing units forming said system, for switching computing function in at least part of computing functions for performing discrete cosine transform and inverse discrete cosine transform for points other than N points, for performing said W point discrete cosine transform and inverse discrete cosine transform in parallel by the computing units forming said system.

2. A discrete cosine transform system as set forth in claim 1, wherein N is powers of 2, and the W points is N/2

3. A discrete cosine transform system as set forth in claim 1, which further has computing modes for performing one of N point discrete cosine transform and N point inverse discrete cosine transform as partial computation of one of K point discrete cosine transform and K point inverse discrete cosine transform, which K point is greater than N point, and for performing partial computation of one of discrete cosine transform and inverse discrete cosine transform for other than N points, and said system comprises storage means for storing results of computation; and computing means for performing partial computation of one of said K point discrete cosine transform and K point inverse discrete cosine transform using the result of computation and a storage value of said storage means.

4. A discrete cosine transform system as set forth in claim 3, wherein N points and K points are powers of 2.

5. A discrete cosine transform system as set forth in claim 1, which has a plurality of systems each having computing mode for performing one of N point discrete cosine transform and N point inverse discrete cosine transform, computing modes for performing one of W point discrete cosine transform and W point inverse discrete cosine transform, which W is smaller than N, and computing mode for performing partial computation of one of K point discrete cosine transform and K point inverse discrete cosine transform which K is greater than N, said systems are adapted for parallel operation, and said discrete cosine transform system includes computing means for performing partial computation one of K point discrete cosine transform and K point inverse discrete cosine transform.

6. A discrete cosine transform system as set forth in claim 5, wherein said N points and K points are powers of 2 and W points is N/2

7. A discrete cosine transform method having one ore more computing modes for performing one of discrete cosine transform and inverse discrete cosine transform for W points which W is positive integer satisfying N>W, in addition to a first computing mode for performing one of discrete cosine transform and inverse discrete cosine transform for N points which N is positive integer, comprising: switching computing function in at least part of computing functions for performing discrete cosine transform and inverse discrete cosine transform for points other than N points, for performing said W point discrete cosine transform and inverse discrete cosine transform in parallel by the computing units forming said system.

8. A discrete cosine transform method as set forth in claim 7, wherein N is powers of 2, and the W points is N/2

9. A discrete cosine transform method as set forth in claim 7, which further has computing modes for performing one of N point discrete cosine transform and N point inverse discrete cosine transform as partial computation of one of K point discrete cosine transform and K point inverse discrete cosine transform, which K point is greater than N point, and for performing partial computation of one of discrete cosine transform and inverse discrete cosine transform for other than N points, and comprising steps of storing results of computation; and performing partial computation of one of said K point discrete cosine transform and K point inverse discrete cosine transform using the result of computation and a storage value of said storage means.

10. A discrete cosine transform method as set forth in claim 9, wherein N points and K points are powers of 2.

11. A discrete cosine transform method as set forth in claim 7, which performs computing mode for performing one of N point discrete cosine transform and N point inverse discrete cosine transform, computing modes for performing one of W point discrete cosine transform and W point inverse discrete cosine transform, which W is smaller than N, and computing mode for performing partial computation of one of K point discrete cosine transform and K point inverse discrete cosine transform which K is greater than N in parallel operation, and said discrete cosine transform system includes computing means for performing partial computation one of K point discrete cosine transform and K point inverse discrete cosine transform.

12. A discrete cosine transform method as set forth in claim 11, wherein said N points and K points are powers of 2 and W points is N/2

13. A discrete cosine transform system comprising: input selecting portion determining a destination for supplying input DCT coefficient; N/2

14. A discrete cosine transform system as set forth in claim 13, wherein said dual mode selective computing portion is replaced with M mode selective computing portion for selection among three or more modes.

15. A discrete cosine transform system as set forth in claim 14, wherein a plurality of said M mode selective computing circuit for parallel operation is included.

16. A discrete cosine transform system comprising: N point inverse discrete cosine transform portion performing either N point inverse discrete cosine transform or partial computation of K (K>N) point inverse discrete cosine transform; storage portion storing result of computation of N point inverse discrete cosine transform in said N point inverse discrete cosine transform portion; and K point inverse discrete cosine transform partial computing portion performing partial computation of K point inverse discrete cosine transform using the result of computation supplied from said storage portion and a result of computation of K point inverse discrete cosine transform partial computation supplied from said N point inverse discrete cosine transform portion.

17. A discrete cosine transform system comprising: a plurality of N point inverse discrete cosine transform portions operable in parallel and performing computation by switching computing function to partial computation of K point (K>N) inverse discrete cosine transform; K point inverse discrete cosine transform partial computing of K point inverse discrete cosine transform using the result of partial computation of K point inverse discrete cosine transform supplied from said plurality of N point inverse discrete cosine transform portions.

Description:

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a discrete cosine transform system and a discrete cosine transform method. More particularly, the invention relates to a system for realizing discrete cosine transform and inverse discrete cosine transform for a plurality of mutually different block sizes in the discrete cosine transform system to be used for compression of an image or the like.

[0003] 2. Description of the Related Art

[0004] Since an image has large information amount, it is typical to transmit or record the image with compression into a predetermined information amount. Upon receipt or playback, the compressed image is decompressed or expanded into an original information amount.

[0005] In general, the image has large amount of low frequency component and small amount of high frequency component. Therefore, if the image is converted into signals of frequency domains, the signals may inclined in the low frequency domain. As a result, by quantizing the signals in low frequency domain with dividing in relatively smaller frequency ranges and by quantizing the signals in the high frequency range with dividing in relatively larger frequency ranges, the image can be compressed with smaller information amount than that before transformation.

[0006] One of frequency conversion system to be employed in a moving picture encoding system is discrete cosine transform (DCT) as orthogonal transformation. In the encoding system employing discrete cosine transform, the image is frequently processed per 8×8 pixels. Therefore, 8×8 two-dimensional discrete cosine transform systems and inverse discrete cosine transform systems as inverse transformation have been developed in large number.

[0007] However, upon performing transformation of resolution in the frequency domain, or encoding employing discrete cosine transform with different block sizes, a system which can perform discrete cosine transform and inverse discrete cosine transform with a plurality of kinds of mutually different block sizes is required.

[0008] Hereinafter, prior art directed to such discrete cosine transform and inverse discrete cosine transform will be discussed. At first, it has been known that two-dimensional discrete cosine transform and two-dimensional inverse discrete cosine transform can be resolved into two times of one-dimensional discrete cosine transform or one-dimensional inverse discrete cosine transform. A system realizing one-dimensional discrete cosine transform and one-dimensional inverse discrete cosine transform becomes important.

[0009] Therefore, discussion will be given for the one-dimensional discrete cosine transform and the one-dimensional inverse discrete cosine transform. N point discrete cosine transform for obtaining N in number of outputs X(

_{k}_{x}_{k}_{k=}

[0010] Here, Σ is sum of n=0 to N−1. X(

[0011] In case of N=8, the foregoing formula (1) may be expressed by the following determinant:

[0012] Here, c_{n}

[0013] On the other hand, from the foregoing formula (2), the following formulae (3) and (4) are established:

[0014] On the other hand, N point one-dimensional inverse discrete cosine transform as inverse transformation of N point one-dimensional discrete cosine transform can be expressed as follow:

_{k}

[0015] Here, Σ is a sum of k=0 to N−1.

[0016] Similarly. in case of N=8, the foregoing equation (5) is expressed by the following determinant:

[0017] From the foregoing determinant (6):

[0018] are established.

[0019] As one example of the conventional system realizing eight points discrete cosine transform and eight point inverse discrete cosine transform is a discrete cosine transform system disclosed in “A 100 MHz 2-D Discrete Cosine Transform Core Processor” (S. Uramoto et al., IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, pp 492 to 499, April, 1992).

[0020] In this system, for performing sum and product operation for matrix operation with the foregoing determinants (3), (4), (7) and (8), in place of large size general purpose adder, memory and adder are used. On the other hand, by inputting eight input signals or eight DCT coefficients in parallel, system capable of further high speed process can be realized.

[0021] One example of the system realizing the eight point discrete cosine transform is shown in

[0022] It should be noted that, in

[0023] In case of the eight point inverse discrete cosine transform in the eight point inverse discrete cosine transform system shown in

[0024] In

[0025] In either case of the system shown in

[0026] Next, in case of N=4, using the determinant for the foregoing expression (1), the following expression is established:

[0027] Similarly, in case of N=4, using the determinant for the foregoing expression (5), the following expression is established:

[0028] The foregoing determinants (9) and (10) are similar to the determinants (3) and (4).

[0029] When N is powers of 2, N point discrete cosine transform and N point inverse discrete cosine transform are frequently calculated using determinants of N/2^{n }^{n }^{n }^{n }^{n}

[0030] Next, consideration is given for the case of the resolution transformation in the frequency domain. As a resolution transformation system in the frequency domain, for example, for the DCT coefficients X(

[0031] When this system is employed, as expressed in the following expression,

_{k}

[0032] it becomes necessary to multiply the DCT coefficients X(k) for 1/{square root}{square root over ( )}2 times, for matching the DCT coefficient of eight point discrete cosine transform in the range of the DCT coefficient of the four point discrete cosine transform. Here, Σ is a sum of k=0 to 3.

[0033] In this case, employing the determinant for the foregoing expression (11), the following determinant is expressed:

[0034] The foregoing determinant (12) is similar to the determinant (7). Therefore, it can be calculated with the same system.

[0035] In the foregoing conventional system, by providing slight modification for the N point discrete cosine transform system and N point inverse discrete cosine transform system, it becomes possible to perform N/2^{n }^{n }

[0036] For example, even in either case of the system shown in

[0037] It can be considered to newly add the arithmetic circuit and to operate the arithmetic circuits in parallel for realizing high speed process. However, in such case, another program of increasing of the scale of the system is inherently encountered.

[0038] The present invention has been worked out for solving the problem set forth above. It is therefore an object of the present invention to provide a discrete cosine transform system and discrete cosine transform method thereof, which enables speeding up and restricts increasing of system scale size associating with speeding up in a system realizing discrete cosine transform and inverse discrete cosine transform for several kinds of different block sizes.

[0039] According to the first aspect of the invention, a discrete cosine transform system having one or more computing modes for performing one of discrete cosine transform and inverse discrete cosine transform for W points which W is positive integer satisfying N>W, in addition to a first computing mode for performing one of discrete cosine transform and inverse discrete cosine transform for N points which N is positive integer, comprises:

[0040] means provided at least a part of computing units forming the system, for switching computing function in at least part of computing functions for performing discrete cosine transform and inverse discrete cosine transform for points other than N points, for performing the W point discrete cosine transform and inverse discrete cosine transform in parallel by the computing units forming the system.

[0041] N may be powers of 2 (2^{n}^{n }^{n}

[0042] the system comprises storage means for storing results of computation; and

[0043] computing means for performing partial computation of one of the K point discrete cosine transform and K point inverse discrete cosine transform using the result of computation and a storage value of the storage means. N points and K points may be powers of 2 (2^{n}^{n }^{n}

[0044] According to the second aspect of the present invention, discrete cosine transform method having one ore more computing modes for performing one of discrete cosine transform and inverse discrete cosine transform for W points which W is positive integer satisfying N>W, in addition to a first computing mode for performing one of discrete cosine transform and inverse discrete cosine transform for N points which N is positive integer, comprises:

[0045] switching computing function in at least part of computing functions for performing discrete cosine transform and inverse discrete cosine transform for points other than N points, for performing the W point discrete cosine transform and inverse discrete cosine transform in parallel by the computing units forming the system.

[0046] The discrete cosine transform method may further have computing modes for performing one of N point discrete cosine transform and N point inverse discrete cosine transform as partial computation of one of K point discrete cosine transform and K point inverse discrete cosine transform, which K point is greater than N point, and for performing partial computation of one of discrete cosine transform and inverse discrete cosine transform for other than N points, and

[0047] comprising steps of

[0048] storing results of computation; and

[0049] performing partial computation of one of the K point discrete cosine transform and K point inverse discrete cosine transform using the result of computation and a storage value of the storage means. The discrete cosine transform method performs computing mode for performing one of N point discrete cosine transform and N point inverse discrete cosine transform, computing modes for performing one of W point discrete cosine transform and W point inverse discrete cosine transform, which W is smaller than N, and computing mode for performing partial computation of one of K point discrete cosine transform and K point inverse discrete cosine transform which K is greater than N in parallel operation, and the discrete cosine transform system includes computing means for performing partial computation one of K point discrete cosine transform and K point inverse discrete cosine transform.

[0050] According to the third aspect of the invention, a discrete cosine transform system comprises:

[0051] input selecting portion determining a destination for supplying input DCT coefficient;

[0052] N/2^{n }^{n }

[0053] dual mode selective computing portion performing partial computation of N point inverse discrete cosine transform or N/2^{n }

[0054] N point inverse discrete cosine transform partial computing portion for performing partial computation of N point inverse discrete cosine transform or multiplication of coefficients from the result of computation supplied from the N/2^{n }

[0055] The duel mode selective computing portion is replaced with M mode selective computing portion for selection among three or more modes. A plurality of the M mode selective computing circuit for parallel operation.

[0056] According to the fourth aspect of the invention, a discrete cosine transform system comprises:

[0057] N point inverse discrete cosine transform portion performing either N point inverse discrete cosine transform or partial computation of K (K>N) point inverse discrete cosine transform;

[0058] storage portion storing result of computation of N point inverse discrete cosine transform in the N point inverse discrete cosine transform portion; and

[0059] K point inverse discrete cosine transform partial computing portion performing partial computation of K point inverse discrete cosine transform using the result of computation supplied from the storage portion and a result of computation of K point inverse discrete cosine transform partial computation supplied from the N point inverse discrete cosine transform portion.

[0060] According to the fifth aspect of the present invention, a discrete cosine transform system comprises:

[0061] a plurality of N point inverse discrete cosine transform portions operable in parallel and performing computation by switching computing function to partial computation of K point (K>N) inverse discrete cosine transform;

[0062] K point inverse discrete cosine transform partial computing of K point inverse discrete cosine transform using the result of partial computation of K point inverse discrete cosine transform supplied from the plurality of N point inverse discrete cosine transform portions.

[0063] In the operation, the conventional eight point inverse discrete cosine transform system takes eight DCT coefficients X(

[0064] Here, in the eight point inverse discrete cosine transform system, the butterfly operation is performed by the butterfly operation portion at the end of the process. However, since computing for x(

[0065] Consideration is given for four point inverse discrete cosine transform by the eight point inverse discrete cosine transform system . The four point inverse discrete cosine transform is included in the eight point inverse discrete cosine transform. Then, as the output of the four point inverse discrete cosine transform, the output of the four point inverse discrete cosine transform portion is output directly. In this case, the output timing is to every one outputs in order to x(

[0066] Next, consideration is given for the case where even in the four point inverse discrete cosine transform, every two original signals are output at every computation. As the simplest method to realize is to add a four point inverse discrete cosine transform portion. However, in this case, the scale of the system is inherently increased.

[0067] In the eight point inverse discrete cosine transform system according to the present invention, two computing functions of partial computing (computing mode

[0068] When two computing modes are employed. In the computing mode

[0069] As set forth above, in the shown embodiment, a plurality of computing functions are switched for realizing parallel operation to obtain the desired output with half of the typical processing period. On the other hand, since the computing unit of the eight point inverse discrete cosine transform partial computing portion

[0070] Accordingly, it becomes possible to realize the system which can perform discrete cosine transform and inverse discrete cosine transform for a plurality of different block sizes. Concerning processes for small block size, high speed process and simplification of system construction are realized by operating the computing units in parallel.

[0071] The present invention will be understood more fully from the detailed description given hereinafter and from the accompanying drawings of the preferred embodiment of the present invention, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only.

[0072] In the drawings:

[0073]

[0074]

[0075]

[0076]

[0077]

[0078]

[0079]

[0080]

[0081]

[0082]

[0083]

[0084]

[0085]

[0086]

[0087]

[0088]

[0089]

[0090]

[0091]

[0092]

[0093]

[0094] The present invention will be discussed hereinafter in detail in terms of the preferred embodiment of the present invention with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to those skilled in the art that the present invention may be practiced without these specific details. In other instance, well-known structure are not shown in detail in order to avoid unnecessary obscurity of the present invention.

[0095] ^{2}^{3}

[0096] The N point inverse discrete cosine transform portion ^{n }^{n }

[0097] At first, in the first computing mode, N in number of DCT coefficients are supplied to the input selecting portion ^{n }

[0098] In the N/2^{n }^{n }

[0099] In the dual mode selective computing unit

[0100] In the N point inverse discrete cosine transform partial computing portion ^{n }

[0101] Next, in the second mode, N/2^{n }^{n }^{n }

[0102] In the N/2^{n }^{n }

[0103] In the dual mode selective computing unit ^{n }^{n }

[0104] In the N point inverse discrete cosine transform partial computing portion ^{n }

[0105]

[0106] The input selecting portion

[0107] The shown embodiment has two computing modes to perform eight point inverse discrete cosine transform in the first computing mode and four point inverse discrete cosine transform in the second computing mode. At first, in the first computing mode, eight DCT coefficients are supplied to input terminals I

[0108] In the input selecting portion

[0109] In the four point inverse discrete cosine transform portion

[0110] In the dual mode selective computing portion

[0111] Next, in the dual mode selective computing portion

[0112] In the eight point inverse discrete cosine transform partial computing portion

[0113] In the second operation mode, four DCT coefficients are supplied as inputs to the input terminals I

[0114] In the four point inverse discrete cosine transform portion

[0115] In this case, the dual mode selective computing portion

[0116] In the eight point inverse discrete cosine transform partial computing portion

[0117]

[0118] The dual mode selective computing unit T

[0119] Here, difference of operation of c

[0120] Operation of the multipliers M^{n }

[0121]

[0122] It should be noted that the foregoing constructions of the dual mode selective computing units T

[0123]

[0124]

[0125] The second embodiment of the eight point inverse discrete cosine transform system according to the present invention is constructed with adders A

[0126] Hereinafter, discussion will be given only for the third mode, in which operation is differentiated from the first embodiment of the eight point inverse discrete cosine transform system according to the present invention. The two point inverse discrete cosine transform can be realized by addition and subtraction of two DCT coefficients and multiplication of c

[0127] In the third computing mode, the multiplier of the dual mode selective computing unit T

[0128] In the adder-subtracter B

[0129] ^{n }^{n }

[0130]

[0131] The third embodiment of the eight point inverse discrete cosine transform system according to the present invention is constructed with adders A

[0132] Hereinafter, discussion will be given only for the second computing mode, in which operation is different from the first embodiment of the present invention in

[0133] Four DCT coefficient is supplied to the input terminals I

[0134] In the adder-subtracter B

[0135] In the adder-subtracter B

[0136]

[0137]

[0138] Hereinafter, discussion will be given for only computing mode for performing K point inverse discrete cosine transform. A K point inverse discrete cosine transform portion

[0139] In the N point inverse discrete cosine transform portion

[0140] Next, the N point inverse discrete cosine transform

[0141] In the K point inverse discrete cosine transform partial computing portion

[0142] In the shown embodiment, since the K point inverse discrete cosine transform greater than N points is realized by the N point inverse discrete cosine transform

[0143]

[0144] In the fourth embodiment of the present invention, the four point inverse discrete cosine transform is constructed with a four point inverse discrete cosine transform portion

[0145] The four point inverse discrete cosine transform

[0146] In the shown embodiment, in the first and second computing modes, operation similar to the first embodiment is performed to realize the four point inverse discrete cosine transform and the two point inverse discrete cosine transform.

[0147] In the third computing mode, at first, in order to perform matrix operation in the determinant (7), the multipliers of the dual mode selective computing units T

[0148] Next, after four point inverse discrete cosine transform, multipliers of the dual mode selective computing units T

[0149] In the eight point inverse discrete cosine transform partial computing portion

[0150]

[0151] Hereinafter, discussion will be given only for computing mode performing K point inverse discrete cosine transform. The K point inverse discrete cosine transform portion

[0152] In the N point inverse discrete cosine transform portions

[0153] In the K point inverse discrete cosine transform partial computing portion

[0154] Since the shown embodiment takes a construction, in which a plurality of N point inverse discrete cosine transform portions

[0155]

[0156] The four point inverse discrete cosine transform portion (

[0157] The shown embodiment has three computing modes to perform four point inverse discrete cosine transform in a first computing mode, two point inverse discrete cosine transform in a second computing mode and eight point inverse discrete cosine transform in a third computing mode. In the first and second computing modes, the operation similar to those in the first embodiment is performed in parallel to realize four point inverse discrete cosine transform and two point inverse discrete cosine transform are realized. It should be noted that, in

[0158] Hereinafter, discussion will be given for the third computing mode. In the four point inverse discrete cosine transform portion

[0159] In the four point inverse discrete cosine transform portion

[0160] In the eight point inverse discrete cosine transform partial computing portion

[0161] FIGS.

[0162] Here, in the eight point inverse discrete cosine transform system

[0163] Consideration is given for four point inverse discrete cosine transform by the eight point inverse discrete cosine transform system

[0164] Next, consideration is given for the case where even in the four point inverse discrete cosine transform, similar to eight point inverse discrete cosine transform, every two original signals are output at every computation. As the simplest method to realize is to add a four point inverse discrete cosine transform portion

[0165] In the eight point inverse discrete cosine transform system

[0166]

[0167] In the computing mode

[0168] As set forth above, in the shown embodiment, a plurality of computing functions are switched for realizing parallel operation to obtain the desired output with half of the typical processing period. On the other hand, since the computing unit of the eight point inverse discrete cosine transform partial computing portion

[0169] Accordingly, it becomes possible to realize the system which can perform discrete cosine transform and inverse discrete cosine transform for a plurality of different block sizes. Concerning processes for small block size, high speed process and simplification of system construction are realized by operating the computing units in parallel.

[0170] As set forth above, by enabling parallel operation of N/2^{n }^{n }

[0171] On the other hand, in a plurality of computing function, since communization of the computing units are made common, increasing of the system scale by addition of the function of the computing units can be eliminated to realize higher processing speed than that in the states.

[0172] As set forth above, according to the present invention, in addition to the first computing modes, in addition thereto, in the discrete cosine transform system having one or more computing modes for performing either discrete cosine transform or inverse discrete cosine transform for W points which is smaller than N points, upon performing either discrete cosine transform or inverse discrete cosine transform in at least a part of computing modes, W point discrete cosine transform or W point inverse discrete cosine transform is performed in parallel, speeding up and restriction of increasing of system scale associating with speeding up can be achieved in the system realizing discrete cosine transform or inverse discrete cosine transform for a plurality of mutually different sizes of black.

[0173] Although the present invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omission and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodied within a scope encompassed and equivalent thereof with respect to the feature set out in the appended claims.